I started my career working on satellites, specifically the checkout, launch, and operations phases. This was a wonderful start to an engineering career because it combines so many interesting fields – structures, electronics, sensors and computing, control systems, propulsion, navigation, communications, and so much more. I could not have asked for a more interesting way to start as a builder. And yet, the desire to learn more about each area has stayed with me through the years. In particular I have always wanted to know the intricacies of how the chips I worked with were made. Silicon in space is fascinating, it has all of the sophistication of computers from ten years ago but with unique requirements to withstand bombardment by cosmic rays, to be robust enough to never require replacement, and the materials to withstand a vacuum. At a cursory level I know that this requires exotic choices like using sapphire substrates or that the designs borrow from common layouts but with additional redundancy. Even still this has never scratched the itch to fully understand how it works.
Recently, with Microsoft Discovery, I have been able to expand my horizons to learn more about parts of silicon design and engineering that have always eluded me. For the first time I was able to walk a chip design problem from spec to physical layout. This project is small, with limited instructions, and far from a cutting edge node. But still, a first for me! And as you will see, the most important part was the learning from walking the process myself, learning more about how this domain of engineering works, and becoming more comfortable working with deep experts in the future.
Chip design is super intimidating to me. Even though the silicon world has a lot of the same culture of deep engineering scrutiny I learned in aerospace, the nuance of it is very intimidating. Regardless, for DAC 2026 I had the opportunity to partner up with the great Professors Liu and Wu to run a workshop on vibe-coding for high-demand engineering processes. Between us we were able to show how to use AI assistance beneficially in both the design and optimization workflows. For my part, I needed to take a rough spec for a RISC-V logic core and a small AI accelerator array to design and layout a chip that would serve as a low-powered embedded device. How cool, if we had continued on through radiation hardening and PCB layout it would be exactly the type of thing I would have looked to have on one of my satellites!
You can find my exploration here: DAC 2026 chip-design project on GitHub. In this project I used Microsoft Discovery to walk this process:
- Take a specification doc to logical C code
- Translate the logic into high level synthesis (HLS) C
- Translate again into a flow of digital signals (RTL)
- And then implement via logical and then physical layout using OpenROAD.
The approach I took for this is a classic engineering process of progressive expansion and detail. The starting point was a spec that I was given by my partners that paints a high-level goal of a RISC-V core with a matrix multiplication accelerator attached. From this I laid out the core logic in logical C code and then expanded that into a more expressive version called high-level synthesis (HLS) C to collect the logical blocks together. At this point I had the logical representation of what the chip should do and needed to start thinking about how to get physical. The first step is to translate this logic to register-transfer level code (RTL). For this project I used Verilog to describe the actual logical devices needed (AND, XOR, etc.). Personally I loved this step as it reminded me a lot of the parametric design space that is somewhere between fully logical spacecraft design and a full physical model.
After finishing the RTL it was time to figure out how to approach actual physical layout and masking of the chip traces. If this were something where I wanted to push the frontier of capability it would be time to start talking to a foundry and using a design kit aligned to a frontier node. Since this is meant to be an open-source example however, I found the OpenROAD open PDK and SKY130 process node as a nice open alternative to test against.
Once running the first physical layout run I got to do my favorite design activity when it’s possible to build a pipeline like this: optimization! Granted, for this project the optimization was fairly limited in scope only modulated a few variables (primarily target clock speed) but even still being able to do parameter sweeps and design iterations autonomously removed the remaining pain points of what was already my favorite part of the design process. If there weren’t a conference presentation deadline I’m sure I would have gone into a much deeper logical-physical optimization loop to create a multidimensional pareto frontier of what was possible….ah, design fun!
Figure 1 - The project flow I used for creating this chip from initial spec to final physical layoutThis process was remarkably straightforward even when limiting myself only to widely available open-source tools and process design kits. With the layout in hand I even tried to do a little bit of optimization for timing and power which was fun as well!
Is this design as good as someone with deep domain expertise could make? Of course not! (Showing how to do that optimization is exactly what Profs. Liu and Wu brought for part two of this discussion). For someone with no domain experience I’m pretty proud of it though and more importantly than anything else it was an introduction to the topic in a hands-on way that would have had a huge time and material cost before. In Prof’ Nan’s own words:
"The experience highlighted an interesting difference between getting a design to work and optimizing it for different use cases. It is important to connect coding agents like Discovery with electronic design automation (EDA) tools, so that synthesis and implementation reports can expose design bottlenecks and inform the next iteration of hardware optimization. This evidence helps develop intuition about which parts of the design matter most and where optimization efforts should be focused. Tools like Discovery can significantly lower the barrier to hardware design by using natural language to support the design process and enable rapid exploration, while still leaving room for expert knowledge to interpret EDA feedback and optimize the design for different application scenarios."
At least for now, I’ve moved on from intimidated by the chip design process to having a modicum of understanding and an even deeper respect for the experts in this field. Before this project I only had an abstract understanding of chip design. At the end, I had a physical-layout design I could continue developing toward fabrication.
Figure 2 - Physical layout blocks of the optimized chipAs an engineer I now have another hugely powerful tool on my toolbench that I can’t wait to use in future projects. Without Discovery at my side to organize my thoughts, manage the project, and execute a lot of the details I would have never gotten to this point.
When a satellite launched we would say “Ad Astra” to wish the rocket and payload along to the stars. With every project I have kept this mentality with me. Now Discovery has me adding “Semper Disco” to add the always learning mindset as I work through each and every problem.